Binary Representation, Logic Circuits, and Instruction Sets

Images, text, and programs are all represented by bit patterns in memory. The CPU does not ordinarily execute an image as an addition instruction because hardware and software determine where to read and how to interpret what is read. Start by separating a bit pattern from its interpretation.

Read binary using place values

A bit has the value 0 or 1. The four bits 1011 have weights 8, 4, 2, and 1 from left to right, so their value is 8+0+2+1=11. There are 2ⁿ possible patterns of n bits. Interpreted as an unsigned integer, they represent values from 0 to 2ⁿ−1. With eight bits, that range is 0 to 255.

Hexadecimal groups four bits into a single digit. Since 1010 is A and 1111 is F, the pattern 1010 1111 is written as 0xAF. This is a more convenient notation, not a change in the value stored in memory. It is useful when reading addresses and masks.

Represent negative integers with two’s complement

In eight-bit two’s complement, the most significant bit has weight −128. Thus, 1111 1111 represents −128+64+32+16+8+4+2+1=−1. Interpreted as an unsigned integer, the same pattern represents 255. The signed range is −128 to 127, so it is not symmetric around zero.

  0000 0101   # 5
invert 1111 1010
add 1  1111 1011   # -5 in 8 bits

0000 0101 + 1111 1011 = 1 0000 0000
keeping the low 8 bits gives 0000 0000

This property allows the same adder circuitry to handle negative numbers. What happens when the result exceeds the representable range is a separate question. For example, the low eight bits of 127+1 are 1000 0000, but the mathematical result 128 is outside the eight-bit signed range. Distinguish the overflow rules of a programming language from those of CPU instructions.

From logical operations to an adder

AND produces 1 when both inputs are 1; OR produces 1 when at least one input is 1; XOR produces 1 when the inputs differ; NOT exchanges 0 and 1. To add two single bits, XOR produces the low sum bit and AND produces the carry. Chaining full adders, which also accept an incoming carry, gives a multibit adder.

A CPU combines an ALU for operations such as logic and addition, registers for temporary values, and a program counter for the position of an instruction to fetch. Instead of doing everything in one place, circuitry selects data paths and operations according to control signals.

An instruction set is a contract with software

An instruction set architecture, or ISA, defines the instructions, registers, and instruction meanings visible to a program. CPUs implementing the same ISA can have different pipeline depths and cache capacities. Separating the ISA from its implementation, the microarchitecture, explains how compatible processors can have different performance.

lw   t0, 0(a0)     # load 32 bits from the address in a0
addi t0, t0, 1     # add 1 to t0
sw   t0, 0(a0)     # store the result at the same address

This is a RISC-V example. In RV32I, loads and stores access memory, while integer arithmetic operates on values in registers. Although these three lines have the single purpose “increment an integer in memory,” reading, computing, and writing are separate instructions. That separation will matter when we examine race conditions.

Check your understanding

Question 1: What does the eight-bit pattern 1111 1110 represent as an unsigned integer and in two’s complement? The answers are 254 and −2. The assigned place values, including that of the most significant bit, determine the interpretation.

Question 2: Will two CPUs that run the same RISC-V program have the same speed? No. Even with the same ISA, their execution circuitry, caches, clock rates, and other implementation details may differ.

Follow how instructions overlap in CPUs, Instruction Cycles, and Pipelines.